Besides line width, some other parameters are also reduced with scaling such as the
MOSFET gate oxide thickness and the power supply voltage. The reductions are chosen
such that the transistor current density (Ion/W) increases with each new node. Also, the smaller transistors and shorter interconnects lead to smaller capacitances. Together, these
changes cause the circuit delays to drop (Eq. 6.7.1). Historically, integrated circuit speed
has increased roughly 30% at each new technology node.