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AMD Polaris 10 R9 480系列跑分公布

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1#
PolyMorph 发表于 2016-5-27 15:01 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 10:36
其实Vega的事情也一样。Vega也跟着Zen进入各种版本流片了。

vega10我觉的能平1080公版就不错了,如果能和1080非公比就算惊喜了
2#
PolyMorph 发表于 2016-5-27 15:08 | 显示全部楼层
本帖最后由 PolyMorph 于 2016-5-27 15:10 编辑
SCE-PhyreEngine 发表于 2016-5-27 15:03
对付1080的是Vega11,目前来看进度倒是不用担心。
Vega10对付的是1080Ti,但从定制版样品性能上看,一个0. ...

咦,不是说Vega11在Vega10之上么,和P11 P10相反
Vega11是4096的话,Vega10估计就是6144sp
3#
PolyMorph 发表于 2016-5-27 15:15 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 15:09
而且旗舰次旗舰都不会在以带数字的命名

老黄估计是低估了vega的性能了,new titan只有3584sp,这样看1080ti不能按套路出牌了,可能是3840也不一定


4#
PolyMorph 发表于 2016-5-27 15:21 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 15:18
帕斯卡的SP效率可不能用老眼光看待

不是有员工资料里爆出greenland 4096sp的信息么,这应该是vega11吧
5#
PolyMorph 发表于 2016-5-27 15:22 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 15:18
帕斯卡的SP效率可不能用老眼光看待

实际性能和架构上看,Maxwell和Pascal就是规格x频率的关系,Pascal频率优势巨大而已
6#
PolyMorph 发表于 2016-5-27 16:10 | 显示全部楼层
本帖最后由 PolyMorph 于 2016-5-27 16:18 编辑
SCE-PhyreEngine 发表于 2016-5-27 15:27
现在看来AMD的GPU部门属于第二类

能耗比提升肯定有,但架构效率就那样了,实测也是如此

之前有消息说145% TTX = greenland(也就是vega11)
现在126% TTX = 1080公版

也就是vega11领先1080公版有15%
和你的消息对的上么




7#
PolyMorph 发表于 2016-5-27 16:43 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 16:24
这个只能到时候等靠谱消息流出,或者官宣。目前消息不能泄露

具体是不能说,vega11对1080有优势可以确认吧
8#
PolyMorph 发表于 2016-5-27 17:13 | 显示全部楼层
本帖最后由 PolyMorph 于 2016-5-27 17:15 编辑
SCE-PhyreEngine 发表于 2016-5-27 16:26
不过可以说的是,名字都叫GCN,但是GCN现在是AMD大的架构框架的代称而已,这个名字不代表技术无进步
...

如果是运用那项新专利,CU就变了




9#
PolyMorph 发表于 2016-5-27 17:20 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 17:18
所以硬件厂商的投资人和合作伙伴,大都不看PPT和文档,他们有自己的专家顾问,他们看的第一步是流片,第二 ...

专利文档是公之于众的,AMD 5月24号申请的
10#
PolyMorph 发表于 2016-5-27 17:34 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 17:28
那种公开的文档的作用就是 有概括性的介绍证明某某申请了什么专利

我的意思是左边北极星,右边织女星,要不然不会有这么大进步的
11#
PolyMorph 发表于 2016-5-27 17:55 | 显示全部楼层
本帖最后由 PolyMorph 于 2016-5-27 17:56 编辑
SCE-PhyreEngine 发表于 2016-5-27 17:41
我另外一个意思是,光看图,咱们也看不出来Vega具体的架构提升措施的优点在哪。。。。
...
Current GPUs (for example, as shown in FIG. 3) only support a single uniform wavefront size (for example, logically supporting 64 thread wide vectors by piping threads through 16 thread wide vector units over four cycles). Vector units of varying widths (for example, as shown in FIG. 4) may be provided to service smaller wavefronts, such as by providing a four thread wide vector unit piped over four cycles to support a wavefront of 16 element vectors. In addition, a high-performance scalar unit may be used to execute critical threads within kernels faster than possible in existing vector pipelines, by executing the same opcodes as the vector units. Such a high performance scalar unit may, in certain instances, allow for a laggard thread (as described above) to be accelerated. By dynamically issuing wavefronts to the execution unit best suited for their size and performance needs, better performance and/or energy efficiency than existing GPU architectures may be obtained.                                  If a wavefront has 64 threads (but only 16 active threads), instead of scheduling the wavefront to a 16 thread wide SIMD unit, the wavefront may be scheduled to a four thread wide SIMD unit. Based on demand (a need basis), the scheduler determines whether to schedule the wavefront to all four thread wide SIMD units or just to a subset of the SIMD units. The threads  migrating  between  these functional  units can have their context (register values) migrated with the help of  software  (using  “spill” and “fill” instructions)  or  with dedicated hardware that helps the migration. Alternately, only the data needed for the upcoming instruction or instructions can be forwarded along with the work through a register­ functional unit crossbar or other interconnection. This determination provides a finer granularity control over how the threads are executed. By dispatching work to a narrower vector unit compared to the baseline wide vector unit, it is possible to execute only as many threads as will actually produce results, thereby saving power.

不同线程数量的wavefront发送给不同宽度的SIMD执行,可以减少空跑率
12#
PolyMorph 发表于 2016-5-27 18:42 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 18:14
这确实是一个方面。也是Fiji里得出的教训

用这个专利greenland VEGA11就不会是4096sp了,和那个泄露信息有矛盾
要么那个信息是假的,要么GCN构架还是原来的样子,或者没有按这个专利图修改
总之还要继续关注动向

13#
PolyMorph 发表于 2016-5-27 20:36 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 20:10
目前Vega到不了流出一些规格的地步




Guys over at 3DCenter discovered a very interesting piece of information. According to Yu Zheng LikenIn profile, who is a research and development manager at AMD, company has been working on new flagship graphics processing unit also known as Greenland or Vega 10.
http://videocardz.com/58237/amds-project-f-is-232mm2-discrete-gpu-made-in-14lpp-process
http://videocardz.com/58665/amds-greenlandvega-10-gpu-to-feature-4096-stream-processors




14#
PolyMorph 发表于 2016-5-27 20:37 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 20:07
媒体又说有4096个SP??
别听那些媒体瞎说。。。。






Guys over at 3DCenter discovered a very interesting piece of information. According to Yu Zheng LikenIn profile, who is a research and development manager at AMD, company has been working on new flagship graphics processing unit also known as Greenland or Vega 10.
15#
PolyMorph 发表于 2016-5-27 21:36 | 显示全部楼层
SCE-PhyreEngine 发表于 2016-5-27 21:24
对付1080和1070,他们确实存在一新一旧两个方案,不过还要看DX12 7-8月更新什么。
定制版用的新的 ...

定制是指PS平台么,P10不是要上PS4.5了么
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