估计IMC差异，我从6700k换成7700k 4*8依旧卡3733，运气好3733 2个错误，偶尔无法开机。
DRAM RTL & IOL: Unlike other timings, DRAM RTL and IOL are measured in memory controller clock cycles rather than DRAM bus cycles. These settings can safely be left on Auto for all normal use. The RTL and IOL parameters define the number of memory controller cycles that elapse before data is returned to the memory controller after a read CAS command is issued. The IOL setting works in conjunction with RTL to fine tune DRAM buffer output latency. Both settings are auto-sensed by the memory controller during the POST process (memory training).
Manual adjustment should not be necessary unless the system is being used in order to obtain maximum DRAM frequency screenshots (limited stability) or if running speeds in excess of DDR3-2400 where some drift may manifest in read/write levelling between AC power cycling of the system (cold BOOT). In such cases, it is worth noting the RTL and IOL values that the system was previously stable at and then apply offsets manually to improve system stability.
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